2009-2011 Microchip Technology Inc. DS22194B-page 23
MCP660/1/2/3/4/5/9
The power de-rating across temperature for an op amp
in a particular package can be easily calculated
(assuming equal power dissipations):
EQUATION 4-5:
Several techniques are available to reduce T
JA
for a
given P
OAmax
:
• Lower
JA
- Use another package
- PCB layout (ground plane, etc.)
- Heat sinks and air flow
• Reduce P
OAmax
- Increase R
L
- Limit I
OUT
(using R
SER
)
- Decrease V
DD
4.3 Distortion
Differential gain (DG) and differential phase (DP) refer
to the non-linear distortion produced by a NTSC or a
phase-alternating line (PAL) video component. Tabl e 1 -
2 and Figure 2-34 show the typical performance of the
MCP661, configured as a gain of +2 amplifier (see
Figure 4-10), when driving one back-matched video
load (150, for 75 cable). Microchip tests use a sine
wave at NTSC’s color sub-carrier frequency of 3.58
MHz, with a 0.286V
P-P
magnitude. The DC input volt-
age is changed over a +0.7V range (positive video) or
a -0.7V range (negative video).
DG is the peak-to-peak change in the AC gain magni-
tude (color hue), as the DC level (luminance) is
changed, in percentile units (%). DP is the peak-to-
peak change in the AC gain phase (color saturation),
as the DC level (luminance) is changed, in degree (°)
units.
4.4 Improving Stability
4.4.1 CAPACITIVE LOADS
Driving large capacitive loads can cause stability prob-
lems for voltage feedback op amps. As the load capac-
itance increases, the phase margin (stability) of the
feedback loop decreases and the closed-loop band-
width is reduced. This produces gain peaking in the fre-
quency response, with overshoot and ringing in the
step response. A unity gain buffer (G = +1) is the most
sensitive to capacitive loads, though all gains show the
same general behavior.
When driving large capacitive loads with these op
amps (e.g., >20 pF when G = +1), a small series resis-
tor at the output (R
ISO
in Figure 4-6) improves the
phase margin of the feedback loop by making the out-
put load resistive at higher frequencies. The bandwidth
generally will be lower than bandwidth without the
capacitive load.
FIGURE 4-6: Output Resistor, R
ISO
Stabilizes Large Capacitive Loads.
Figure 4-7 gives recommended R
ISO
values for differ-
ent capacitive loads and gains. The x-axis is the nor-
malized load capacitance (C
L
/G
N
), where G
N
is the
circuit’s noise gain. For non-inverting gains, G
N
and the
Signal Gain are equal. For inverting gains, G
N
is
1+|Signal Gain| (e.g., -1 V/V gives G
N
= +2 V/V).
FIGURE 4-7: Recommended R
ISO
Values
for Capacitive Loads.
After selecting R
ISO
for the circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify R
ISO
’s value until the
response is reasonable. Bench evaluation and simula-
tions with the MCP660/1/2/3/4/5/9 SPICE macro model
are helpful.
n
JA
T
Jmax
– T
A
P
OAmax
Where:
T
Jmax
= absolute max. junction temperature
1
10
100
1.E-11 1.E-10 1.E-09 1.E-08
Normalized Capacitance; C
L
/G
N
(F)
Recommended R
ISO
(Ω)
G
N
= +1
G
N
+2
10p 100p 1n 10n
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