Microchip Technology Zena Especificaciones Pagina 1

© 2007 Microchip Technology Inc. DS41190EPIC12F629/675Data Sheet8-Pin, Flash-Based 8-BitCMOS Microcontrollers*8-bit, 8-pin Devices Protected by Micro

PIC12F629/675DS41190E-page 8 © 2007 Microchip Technology Inc.2.2.2 SPECIAL FUNCTION REGISTERSThe Special Function registers are registers used bythe

PIC12F629/675DS41190E-page 98 © 2007 Microchip Technology Inc.TABLE 12-6: COMPARATOR SPECIFICATIONSTABLE 12-7: COMPARATOR VOLTAGE REFERENCE SPECIFIC

© 2007 Microchip Technology Inc. DS41190E-page 99PIC12F629/675TABLE 12-8: PIC12F675 A/D CONVERTER CHARACTERISTICS:Param No.Sym Characteristic Min Typ†

PIC12F629/675DS41190E-page 100 © 2007 Microchip Technology Inc.FIGURE 12-10: PIC12F675 A/D CONVERSION TIMING (NORMAL MODE)TABLE 12-9: PIC12F675 A/D

© 2007 Microchip Technology Inc. DS41190E-page 101PIC12F629/675FIGURE 12-11: PIC12F675 A/D CONVERSION TIMING (SLEEP MODE)TABLE 12-10: PIC12F675 A/D CO

PIC12F629/675DS41190E-page 102 © 2007 Microchip Technology Inc.NOTES:

© 2007 Microchip Technology Inc. DS41190E-page 103PIC12F629/67513.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLESThe graphs and tables provided in this

PIC12F629/675DS41190E-page 104 © 2007 Microchip Technology Inc.FIGURE 13-3: TYPICAL IPD vs. VDD OVER TEMP (+125°C)FIGURE 13-4: MAXIMUM IPD vs. VDD O

© 2007 Microchip Technology Inc. DS41190E-page 105PIC12F629/675FIGURE 13-5: MAXIMUM IPD vs. VDD OVER TEMP (+85°C) FIGURE 13-6: MAXIMUM IPD vs. VDD OVE

PIC12F629/675DS41190E-page 106 © 2007 Microchip Technology Inc.FIGURE 13-7: TYPICAL IPD WITH BOD ENABLED vs. VDD OVER TEMP (-40°C TO +125°C)FIGURE 1

© 2007 Microchip Technology Inc. DS41190E-page 107PIC12F629/675FIGURE 13-9: TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (-40°C TO +25°C)FIGURE 13-1

© 2007 Microchip Technology Inc. DS41190E-page 9PIC12F629/675TABLE 2-1: SPECIAL FUNCTION REGISTERS SUMMARYAddress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B

PIC12F629/675DS41190E-page 108 © 2007 Microchip Technology Inc.FIGURE 13-11: TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (+125°C)FIGURE 13-12: TY

© 2007 Microchip Technology Inc. DS41190E-page 109PIC12F629/675FIGURE 13-13: TYPICAL IPD WITH CVREF ENABLED vs. VDD OVER TEMP (-40°C TO +125°C)FIGURE

PIC12F629/675DS41190E-page 110 © 2007 Microchip Technology Inc.FIGURE 13-15: MAXIMUM AND MINIMUM INTOSC FREQ vs. TEMPERATURE WITH 0.1μF AND 0.01μF D

© 2007 Microchip Technology Inc. DS41190E-page 111PIC12F629/675FIGURE 13-17: TYPICAL WDT PERIOD vs. VDD (-40°C TO +125°C)WDT Time-out05101520253035404

PIC12F629/675DS41190E-page 112 © 2007 Microchip Technology Inc.NOTES:

© 2007 Microchip Technology Inc. DS41190E-page 113PIC12F629/67514.0 PACKAGING INFORMATION14.1 Package Marking Information XXXXXNNN8-Lead PDIP

PIC12F629/675DS41190E-page 114 © 2007 Microchip Technology Inc.14.2 Package DetailsThe following sections give the technical details of the packages

© 2007 Microchip Technology Inc. DS41190E-page 115PIC12F629/6758-Lead Plastic Small Outline (SN or OA) – Narrow, 3.90 mm Body [SOIC]Notes:1. Pin 1 vis

PIC12F629/675DS41190E-page 116 © 2007 Microchip Technology Inc.8-Lead Plastic Dual Flat, No Lead Package (MF) – 6x5 mm Body [DFN-S] Notes:1. Pin 1 v

© 2007 Microchip Technology Inc. DS41190E-page 117PIC12F629/675APPENDIX A: DATA SHEET REVISION HISTORYRevision AThis is a new data sheet.Revision BAdd

PIC12F629/675DS41190E-page 10 © 2007 Microchip Technology Inc.Bank 180h INDF(1)Addressing this Location uses Contents of FSR to Address Data Memory

PIC12F629/675DS41190E-page 118 © 2007 Microchip Technology Inc.APPENDIX C: DEVICE MIGRATIONSThis section is intended to describe the functional ande

© 2007 Microchip Technology Inc. DS41190E-page 119PIC12F629/675INDEX AA/D ...

PIC12F629/675DS41190E-page 120 © 2007 Microchip Technology Inc.BSF ... 71BTF

© 2007 Microchip Technology Inc. DS41190E-page 121PIC12F629/675Prescaler... 31Timer1

PIC12F629/675DS41190E-page 122 © 2007 Microchip Technology Inc.NOTES:

© 2007 Microchip Technology Inc. DS41190E-page 123PIC12F629/675THE MICROCHIP WEB SITEMicrochip provides online support via our WWW site atwww.microchi

PIC12F629/675DS41190E-page 124 © 2007 Microchip Technology Inc.READER RESPONSEIt is our intention to provide you with the best documentation possible

© 2007 Microchip Technology Inc. DS41190E-page 125PIC12F629/675PRODUCT IDENTIFICATION SYSTEMTo order or obtain information, e.g., on pricing or delive

DS41190E-page 126 © 2007 Microchip Technology Inc.AMERICASCorporate Office2355 West Chandler Blvd.Chandler, AZ 85224-6199Tel: 480-792-7200 Fax: 48

© 2007 Microchip Technology Inc. DS41190E-page 11PIC12F629/6752.2.2.1 STATUS RegisterThe STATUS register, shown in Register 2-1, contains:• the arithm

PIC12F629/675DS41190E-page 12 © 2007 Microchip Technology Inc.2.2.2.2 OPTION RegisterThe OPTION register is a readable and writableregister, which c

© 2007 Microchip Technology Inc. DS41190E-page 13PIC12F629/6752.2.2.3 INTCON RegisterThe INTCON register is a readable and writableregister, which con

PIC12F629/675DS41190E-page 14 © 2007 Microchip Technology Inc.2.2.2.4 PIE1 RegisterThe PIE1 register contains the interrupt enable bits, asshown in

© 2007 Microchip Technology Inc. DS41190E-page 15PIC12F629/6752.2.2.5 PIR1 RegisterThe PIR1 register contains the interrupt flag bits, asshown in Regi

PIC12F629/675DS41190E-page 16 © 2007 Microchip Technology Inc.2.2.2.6 PCON RegisterThe Power Control (PCON) register contains flag bitsto differenti

© 2007 Microchip Technology Inc. DS41190E-page 17PIC12F629/6752.3 PCL and PCLATHThe program counter (PC) is 13-bits wide. The low bytecomes from the P

DS41190E-page ii © 2007 Microchip Technology Inc.Information contained in this publication regarding deviceapplications and the like is provided only

PIC12F629/675DS41190E-page 18 © 2007 Microchip Technology Inc.2.4 Indirect Addressing, INDF and FSR Registers The INDF register is not a physical

© 2007 Microchip Technology Inc. DS41190E-page 19PIC12F629/6753.0 GPIO PORTThere are as many as six general purpose I/O pinsavailable. Depending on wh

PIC12F629/675DS41190E-page 20 © 2007 Microchip Technology Inc.REGISTER 3-2: TRISIO — GPIO TRI-STATE REGISTER (ADDRESS: 85h) REG

© 2007 Microchip Technology Inc. DS41190E-page 21PIC12F629/6753.2.2 INTERRUPT-ON-CHANGEEach of the GPIO pins is individually configurable as aninterru

PIC12F629/675DS41190E-page 22 © 2007 Microchip Technology Inc.3.3 Pin Descriptions and DiagramsEach GPIO pin is multiplexed with other functions. Th

© 2007 Microchip Technology Inc. DS41190E-page 23PIC12F629/6753.3.3 GP2/AN2/T0CKI/INT/COUTFigure 3-2 shows the diagram for this pin. The GP2 pinis con

PIC12F629/675DS41190E-page 24 © 2007 Microchip Technology Inc.3.3.5 GP4/AN3/T1G/OSC2/CLKOUTFigure 3-4 shows the diagram for this pin. The GP4 pinis

© 2007 Microchip Technology Inc. DS41190E-page 25PIC12F629/675TABLE 3-1: SUMMARY OF REGISTERS ASSOCIATED WITH GPIOAddress Name Bit 7 Bit 6 Bit 5 Bit 4

PIC12F629/675DS41190E-page 26 © 2007 Microchip Technology Inc.NOTES:

© 2007 Microchip Technology Inc. DS41190E-page 27PIC12F629/6754.0 TIMER0 MODULEThe Timer0 module timer/counter has the followingfeatures:• 8-bit timer

© 2007 Microchip Technology Inc. DS41190E-page 1PIC12F629/675High Performance RISC CPU:• Only 35 instructions to learn- All single cycle instructions

PIC12F629/675DS41190E-page 28 © 2007 Microchip Technology Inc.4.3 Using Timer0 with an External ClockWhen no prescaler is used, the external clock i

© 2007 Microchip Technology Inc. DS41190E-page 29PIC12F629/6754.4 PrescalerAn 8-bit counter is available as a prescaler for theTimer0 module, or as a

PIC12F629/675DS41190E-page 30 © 2007 Microchip Technology Inc.5.0 TIMER1 MODULE WITH GATE CONTROLThe PIC12F629/675 devices have a 16-bit timer.Figur

© 2007 Microchip Technology Inc. DS41190E-page 31PIC12F629/6755.1 Timer1 Modes of OperationTimer1 can operate in one of three modes:• 16-bit timer wit

PIC12F629/675DS41190E-page 32 © 2007 Microchip Technology Inc.REGISTER 5-1: T1CON — TIMER1 CONTROL REGISTER (ADDRESS: 10h) U-0 R/W-0 R/W-0

© 2007 Microchip Technology Inc. DS41190E-page 33PIC12F629/6755.4 Timer1 Operation in Asynchronous Counter ModeIf control bit T1SYNC (T1CON<2>)

PIC12F629/675DS41190E-page 34 © 2007 Microchip Technology Inc.NOTES:

© 2007 Microchip Technology Inc. DS41190E-page 35PIC12F629/6756.0 COMPARATOR MODULEThe PIC12F629/675 devices have one analogcomparator. The inputs to

PIC12F629/675DS41190E-page 36 © 2007 Microchip Technology Inc.6.1 Comparator OperationA single comparator is shown in Figure 6-1, along withthe rela

© 2007 Microchip Technology Inc. DS41190E-page 37PIC12F629/6756.2 Comparator ConfigurationThere are eight modes of operation for the comparator.The CM

PIC12F629/675DS41190E-page 2 © 2007 Microchip Technology Inc.Pin DiagramsVSSVDDGP5/T1CKI/OSC1/CLKINGP4/AN3/T1G/OSC2/CLKOUTGP3/MCLR/VPPGP0/AN0/CIN+/I

PIC12F629/675DS41190E-page 38 © 2007 Microchip Technology Inc.6.3 Analog Input Connection ConsiderationsA simplified circuit for an analog input is

© 2007 Microchip Technology Inc. DS41190E-page 39PIC12F629/6756.5 Comparator ReferenceThe comparator module also allows the selection of aninternally

PIC12F629/675DS41190E-page 40 © 2007 Microchip Technology Inc.REGISTER 6-2: VRCON — VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 99h)

© 2007 Microchip Technology Inc. DS41190E-page 41PIC12F629/6757.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE (PIC12F675 ONLY)The analog-to-digital conve

PIC12F629/675DS41190E-page 42 © 2007 Microchip Technology Inc.TABLE 7-1: TAD vs. DEVICE OPERATING FREQUENCIES 7.1.5 STARTING A CONVERSIONThe A/D co

© 2007 Microchip Technology Inc. DS41190E-page 43PIC12F629/675REGISTER 7-1: ADCON0 — A/D CONTROL REGISTER (ADDRESS: 1Fh) R/W-0 R/W-0 U-0 U-0 R/W-0 R/

PIC12F629/675DS41190E-page 44 © 2007 Microchip Technology Inc.REGISTER 7-2: ANSEL — ANALOG SELECT REGISTER (ADDRESS: 9Fh) U-0 R/W-0

© 2007 Microchip Technology Inc. DS41190E-page 45PIC12F629/6757.2 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy

PIC12F629/675DS41190E-page 46 © 2007 Microchip Technology Inc.7.3 A/D Operation During SLEEPThe A/D converter module can operate during SLEEP.This r

© 2007 Microchip Technology Inc. DS41190E-page 47PIC12F629/6758.0 DATA EEPROM MEMORYThe EEPROM data memory is readable and writableduring normal opera

© 2007 Microchip Technology Inc. DS41190E-page 3PIC12F629/675Table of Contents1.0 Device Overview...

PIC12F629/675DS41190E-page 48 © 2007 Microchip Technology Inc.8.1 EEADR The EEADR register can address up to a maximum of128 bytes of data EEPROM. O

© 2007 Microchip Technology Inc. DS41190E-page 49PIC12F629/6758.3 READING THE EEPROM DATA MEMORYTo read a data memory location, the user must writethe

PIC12F629/675DS41190E-page 50 © 2007 Microchip Technology Inc.8.7 DATA EEPROM OPERATION DURING CODE PROTECTData memory can be code protected by prog

© 2007 Microchip Technology Inc. DS41190E-page 51PIC12F629/6759.0 SPECIAL FEATURES OF THE CPUCertain special circuits that deal with the needs of real

PIC12F629/675DS41190E-page 52 © 2007 Microchip Technology Inc.9.1 Configuration BitsThe configuration bits can be programmed (read as '0')

© 2007 Microchip Technology Inc. DS41190E-page 53PIC12F629/6759.2 Oscillator Configurations9.2.1 OSCILLATOR TYPESThe PIC12F629/675 can be operated in

PIC12F629/675DS41190E-page 54 © 2007 Microchip Technology Inc.9.2.3 EXTERNAL CLOCK INFor applications where a clock is already availableelsewhere, u

© 2007 Microchip Technology Inc. DS41190E-page 55PIC12F629/6759.3 RESETThe PIC12F629/675 differentiates between variouskinds of RESET: a) Power-on Res

PIC12F629/675DS41190E-page 56 © 2007 Microchip Technology Inc.9.3.1 MCLRPIC12F629/675 devices have a noise filter in theMCLR Reset path. The filter

© 2007 Microchip Technology Inc. DS41190E-page 57PIC12F629/6759.3.5 BROWN-OUT DETECT (BOD)The PIC12F629/675 members have on-chip Brown-outDetect circu

PIC12F629/675DS41190E-page 4 © 2007 Microchip Technology Inc.NOTES:

PIC12F629/675DS41190E-page 58 © 2007 Microchip Technology Inc.TABLE 9-3: TIME-OUT IN VARIOUS SITUATIONSTABLE 9-4: STATUS/PCON BITS AND THEIR SIGNIFI

© 2007 Microchip Technology Inc. DS41190E-page 59PIC12F629/675TABLE 9-7: INITIALIZATION CONDITION FOR REGISTERSRegister AddressPower-on Reset•MCLR Res

PIC12F629/675DS41190E-page 60 © 2007 Microchip Technology Inc.FIGURE 9-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1FIGURE 9-8: TI

© 2007 Microchip Technology Inc. DS41190E-page 61PIC12F629/6759.4 InterruptsThe PIC12F629/675 has 7 sources of interrupt: • External Interrupt GP2/INT

PIC12F629/675DS41190E-page 62 © 2007 Microchip Technology Inc.FIGURE 9-10: INTERRUPT LOGIC TMR1IFTMR1IECMIFCMIET0IFT0IEINTFINTEGPIFGPIEGIEPEIEWake-u

© 2007 Microchip Technology Inc. DS41190E-page 63PIC12F629/6759.4.1 GP2/INT INTERRUPTExternal interrupt on GP2/INT pin is edge-triggered;either rising

PIC12F629/675DS41190E-page 64 © 2007 Microchip Technology Inc.TABLE 9-8: SUMMARY OF INTERRUPT REGISTERS9.5 Context Saving During InterruptsDuring an

© 2007 Microchip Technology Inc. DS41190E-page 65PIC12F629/675FIGURE 9-12: WATCHDOG TIMER BLOCK DIAGRAMTABLE 9-9: SUMMARY OF WATCHDOG TIMER REGISTERST

PIC12F629/675DS41190E-page 66 © 2007 Microchip Technology Inc.9.7 Power-Down Mode (SLEEP)The Power-down mode is entered by executing aSLEEP instruct

© 2007 Microchip Technology Inc. DS41190E-page 67PIC12F629/6759.8 Code ProtectionIf the code protection bit(s) have not beenprogrammed, the on-chip pr

© 2007 Microchip Technology Inc. DS41190E-page 5PIC12F629/6751.0 DEVICE OVERVIEWThis document contains device specific information forthe PIC12F629/67

PIC12F629/675DS41190E-page 68 © 2007 Microchip Technology Inc.NOTES:

© 2007 Microchip Technology Inc. DS41190E-page 69PIC12F629/67510.0 INSTRUCTION SET SUMMARYThe PIC12F629/675 instruction set is highly orthogonaland is

PIC12F629/675DS41190E-page 70 © 2007 Microchip Technology Inc.TABLE 10-2: PIC12F629/675 INSTRUCTION SET Mnemonic,OperandsDescription Cycles14-Bit

© 2007 Microchip Technology Inc. DS41190E-page 71PIC12F629/67510.2 Instruction Descriptions ADDLW Add Literal and WSyntax: [label] ADDLW kOperand

PIC12F629/675DS41190E-page 72 © 2007 Microchip Technology Inc.CALL Call SubroutineSyntax: [ label ] CALL kOperands: 0 ≤ k ≤ 2047Operation: (PC)+

© 2007 Microchip Technology Inc. DS41190E-page 73PIC12F629/675DECFSZ Decrement f, Skip if 0Syntax: [ label ] DECFSZ f,dOperands: 0 ≤ f ≤ 127d ∈ [0

PIC12F629/675DS41190E-page 74 © 2007 Microchip Technology Inc.MOVF Move fSyntax: [ label ] MOVF f,dOperands: 0 ≤ f ≤ 127d ∈ [0,1]Operation: (f)

© 2007 Microchip Technology Inc. DS41190E-page 75PIC12F629/675RLF Rotate Left f through CarrySyntax: [ label ] RLF f,dOperands: 0 ≤ f ≤ 127d ∈ [0,1

PIC12F629/675DS41190E-page 76 © 2007 Microchip Technology Inc.SWAPF Swap Nibbles in fSyntax: [ label ] SWAPF f,dOperands: 0 ≤ f ≤ 127d ∈ [0,1]Opera

© 2007 Microchip Technology Inc. DS41190E-page 77PIC12F629/67511.0 DEVELOPMENT SUPPORTThe PIC® microcontrollers are supported with a fullrange of hard

PIC12F629/675DS41190E-page 6 © 2007 Microchip Technology Inc.TABLE 1-1: PIC12F629/675 PINOUT DESCRIPTIONName FunctionInputTypeOutputTypeDescription

PIC12F629/675DS41190E-page 78 © 2007 Microchip Technology Inc.11.2 MPASM AssemblerThe MPASM Assembler is a full-featured, universalmacro assembler for

© 2007 Microchip Technology Inc. DS41190E-page 79PIC12F629/67511.7 MPLAB ICE 2000 High-Performance In-Circuit EmulatorThe MPLAB ICE 2000 In-Circuit Em

PIC12F629/675DS41190E-page 80 © 2007 Microchip Technology Inc.11.11 PICSTART Plus Development ProgrammerThe PICSTART Plus Development Programmer is an

© 2007 Microchip Technology Inc. DS41190E-page 81PIC12F629/67512.0 ELECTRICAL SPECIFICATIONSAbsolute Maximum Ratings†Ambient temperature under bias...

PIC12F629/675DS41190E-page 82 © 2007 Microchip Technology Inc.FIGURE 12-1: PIC12F629/675 WITH A/D DISABLED VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +12

© 2007 Microchip Technology Inc. DS41190E-page 83PIC12F629/675FIGURE 12-3: PIC12F675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH, 0°C ≤ TA ≤ +125°C5.52.0

PIC12F629/675DS41190E-page 84 © 2007 Microchip Technology Inc.12.1 DC Characteristics: PIC12F629/675-I (Industrial), PIC12F629/675-E (Extended) DC

© 2007 Microchip Technology Inc. DS41190E-page 85PIC12F629/67512.2 DC Characteristics: PIC12F629/675-I (Industrial)Standard Operating Conditions (unle

PIC12F629/675DS41190E-page 86 © 2007 Microchip Technology Inc.12.3 DC Characteristics: PIC12F629/675-I (Industrial)Standard Operating Conditions (un

© 2007 Microchip Technology Inc. DS41190E-page 87PIC12F629/67512.4 DC Characteristics: PIC12F629/675-E (Extended)Standard Operating Conditions (unless

© 2007 Microchip Technology Inc. DS41190E-page 7PIC12F629/6752.0 MEMORY ORGANIZATION2.1 Program Memory OrganizationThe PIC12F629/675 devices have a 13

PIC12F629/675DS41190E-page 88 © 2007 Microchip Technology Inc.12.5 DC Characteristics: PIC12F629/675-E (Extended)Standard Operating Conditions (unle

© 2007 Microchip Technology Inc. DS41190E-page 89PIC12F629/67512.6 DC Characteristics: PIC12F629/675-I (Industrial), PIC12F629/675-E (Extended) DC CHA

PIC12F629/675DS41190E-page 90 © 2007 Microchip Technology Inc.12.7 DC Characteristics: PIC12F629/675-I (Industrial), PIC12F629/675-E (Extended) (Con

© 2007 Microchip Technology Inc. DS41190E-page 91PIC12F629/67512.8 TIMING PARAMETER SYMBOLOGYThe timing parameter symbols have been created withone of

PIC12F629/675DS41190E-page 92 © 2007 Microchip Technology Inc.12.9 AC CHARACTERISTICS: PIC12F629/675 (INDUSTRIAL, EXTENDED)FIGURE 12-5: EXTERNAL CLO

© 2007 Microchip Technology Inc. DS41190E-page 93PIC12F629/675TABLE 12-2: PRECISION INTERNAL OSCILLATOR PARAMETERS Param No.Sym CharacteristicFreqTol

PIC12F629/675DS41190E-page 94 © 2007 Microchip Technology Inc.FIGURE 12-6: CLKOUT AND I/O TIMING TABLE 12-3: CLKOUT AND I/O TIMING REQUIREMENTS

© 2007 Microchip Technology Inc. DS41190E-page 95PIC12F629/675FIGURE 12-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMINGF

PIC12F629/675DS41190E-page 96 © 2007 Microchip Technology Inc.TABLE 12-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROW

© 2007 Microchip Technology Inc. DS41190E-page 97PIC12F629/675FIGURE 12-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGSTABLE 12-5: TIMER0 AND TIMER1 EXTER