Microchip Technology dsPIC33F Family Especificaciones descargar pdf (Pagina 11)

Section 43. High-Speed PWM

High-Speed PWM

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — PCLKDIV<2:0>

(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-3 Unimplemented: Read as ‘0’

bit 2-0 PCLKDIV<2:0>: PWM Input Clock Prescaler (Divider) Select bits

(1)

111 = Reserved

110 = Divide by 64, maximum PWM timing resolution

101 = Divide by 32, maximum PWM timing resolution

100 = Divide by 16, maximum PWM timing resolution

011 = Divide by 8, maximum PWM timing resolution

010 = Divide by 4, maximum PWM timing resolution

001 = Divide by 2, maximum PWM timing resolution

000 = Divide by 1, maximum PWM timing resolution (power-on default)

Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will

yield unpredictable results.

Note: The PWM input clock prescaler will affect all timing parameters of the PWM module, including period, duty

cycle, phase, dead-time, triggers, leading-edge blanking and PWM capture.

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Microchip Technology dsPIC33F Family Especificaciones Pagina 11