Microchip Technology Audio Digital-to-Analog Converter Manual de usuario descargar pdf (Pagina 24)

Interrupts and Status

z Two Interrupts (one for each channel)

z Interrupt Conditions

− FIFO is not full

− FIFO is empty

z FIFO Status

− FIFO is Full

− FIFO is Empty

DAC reads data from FIFO/DACDFLT register every

256 DAC clock cycles.

The Audio DAC provides two interrupts, one for each channel. Depending on the

setting of the interrupt configuration bits (LITYPE for the left channel and RITYPE

for the right channel) in the DAC Status Register (DACxSTAT), the DAC interrupt

is triggered by either a “FIFO EMPTY” or “FIFO NOT FULL” condition. The FIFO

empty interrupt can be used with the Audio DAC to maximize throughput while

minimizing the impact of interrupts on the CPU. The FIFO EMPTY interrupt is the

simplest and preferred interrupt method for use with DMA. The FIFO NOT FULL

interrupt is used in applications without DMA to minimize the occurrence of DAC

under-run. This interrupt can also be used with DMA, but additional software

support is required.

Each channel also has two status bits that can be read to indicate the status of the

FIFO. The Right Channel Full (RFULL) and the Left Channel Full (LFULL) bits in

the DACxSTAT register indicate that the FIFO is FULL. The Right Channel Empty

(REMPTY) and the Left Channel Empty (LEMPTY) bits in the DACxSTAT

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Microchip Technology Audio Digital-to-Analog Converter Manual de usuario Pagina 24