
29
© 2007 Microchip Technology Incorporated. All Rights Reserved. Audio Digital-to-Analog Converter Slide 29
Output First
Sample
Output First
Sample
DAC Interaction without DMA
After 256 DAC clock cycles data will be read from the FIFOs and will begin being
processed by the D/A.
Once data is transferred from the FIFO another DAC interrupt is generated and the
CPU will again process the interrupt and transfer new data into the DAC data
registers. This process continues until the DAC module is shut down or if the device
is put into sleep mode.
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