Microchip Technology dsPIC33F Family Manual de usuario Pagina 31

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© 2005 Microchip Technology Inc. Preliminary DS70155C-page 29
dsPIC33F
Figure 8-4 is a block diagram of the DCI module. The
DCI can support up to 16 time slots in a data frame for
a maximum frame size of 256 bits. There are control
bits for each time slot in the data frame that determine
whether the DCI will transmit/receive during the time
slot. The DCI module supports DMA data transfers.
FIGURE 8-4: DCI MODULE BLOCK DIAGRAM
8.8 SPI™ Module
The Serial Peripheral Interface (SPI) module is a
synchronous serial interface for communicating with
other peripheral or microcontroller devices such as
serial EEPROMs, shift registers, display drivers, A/D
Converters, etc. It is compatible with Motorola
®
SPI and
SIOP interfaces.
This SPI module includes all SPI modes. A Frame
Synchronization mode is also included for support of
voice band codecs.
Four pins make up the serial interface: SDI, Serial Data
Input; SDO, Serial Data Output; SCK, Shift Clock Input
or Output; SS
, Active-Low Slave Select, which also
serves as the FSYNC (Frame Synchronization Pulse).
A device set up as an SPI master provides the serial
communication clock signal on its SCK pin.
A series of 8 or 16 clock pulses (depending on mode)
shift out the 8 or 16 bits (depending on whether a byte
or word is being transferred) and simultaneously shift in
8 or 16 bits of data from the SDI pin. An interrupt is
generated when the transfer is complete.
Slave select synchronization allows selective enabling
of SPI slave devices, which is particularly useful when
a single master is connected to multiple slaves.
The SPI1 and SPI2 modules support DMA data
transfers.
BCG Control Bits
16-Bit Data Bus
Sample Rate
Generator
CSCKD
COFSD
DCI Buffer
Frame
Synchronization
Generator
Control Unit
DCI Shift Register
Receive Buffer
Registers w/Shadow
FOSC/4
Word Size Selection bits
Frame Length Selection bits
DCI Mode Selection bits
CSCK
COFS
CSDI
CSDO
15
0
Transmit Buffer
Registers w/Shadow
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