Microchip Technology dsPIC33F Family Manual de usuario descargar pdf (Pagina 32)

dsPIC33F

8.9 UART Module

The UART is a full-duplex asynchronous system that

can communicate with peripheral devices, such as

personal computers, RS-232 and RS-485 interfaces.

The dsPIC33F devices have one or more UARTs.

The key features of the UART module are:

• Full-duplex operation with 8 or 9-bit data

• Even, odd or no parity options (for 8-bit data)

• One or two Stop bits

• Fully integrated Baud Rate Generator (BRG) with

16-bit prescaler

• Baud rates range from up to 10 Mbps and down to

38 Hz at 40 MIPS

• 4-character deep transmit data buffer

• 4-character deep receive data buffer

• Parity, framing and buffer overrun error detection

•Full IrDA

support, including hardware encoding

and decoding of IrDA

messages

• LIN bus support

- Auto wake-up from Sleep or Idle mode on

Start bit detect

- Auto-baud detection

- Break character support

• Support for interrupt on address detect (9th bit = 1)

• Separate transmit and receive interrupts

- On transmission of 1 or 4 characters

- On reception of 1, 3 and 4 characters

• Loopback mode for diagnostics

The UART1 and UART2 modules support DMA data

transfers.

8.10 I

C™ Module

The I

C module is a synchronous serial interface, useful

for communicating with other peripheral or

microcontroller devices. These peripheral devices may

be serial EEPROMs, shift registers, display drivers, A/D

Converters, etc.

The Inter-Integrated Circuit (I

C) module offers full

hardware support for both slave and multi-master

operations.

The key features of the I

C module are:

•I

C slave operation supports 7 and 10-bit address

•I

C master operation supports 7 and 10-bit address

•I

C port allows bidirectional transfers between

master and slaves

• Serial clock synchronization for I

C port can be

used as a handshake mechanism to suspend and

resume serial transfer (serial clock stretching)

•I

C supports multi-master operation; detects bus

collision and will arbitrate accordingly

• Slew rate control for 100 kHz and 400 kHz bus speeds

In I

C mode, pin SCL is clock and pin SDA is data. The

module will override the data direction bits for these pins.

8.11 Controller Area Network (CAN)

Module

The Controller Area Network (CAN) module is a serial

interface useful for communicating with other CAN

modules or microcontroller devices. This interface/

protocol was designed to allow communications within

noisy environments.

The CAN module is a communication controller

implementing the CAN 2.0 A/B protocol, as defined in

the BOSCH specification. The module supports

CAN 1.2, CAN 2.0A, CAN2.0B Passive and CAN 2.0B

Active versions of the protocol. Details of these protocols

can be found in the BOSCH CAN specification.

The CAN module features:

• Implementation of the CAN protocol CAN 1.2,

CAN 2.0A and CAN 2.0B

• Standard and extended data frames

• Data lengths of 0-8 bytes

• Programmable bit rate up to 1 Mbit/sec

• Automatic response to remote frames

• Up to 16 receive buffers in DMA RAM

• FIFO Buffer mode (up to 64 messages deep)

• 16 full (standard/extended identifier) acceptance

filters

• 3 full acceptance filter masks

• Up to 8 transmit buffers in DMA RAM

• DMA can be used for transmission and reception

• Programmable wake-up functionality with

integrated low-pass filter

• Programmable Loopback mode supports self-test

operation

• Signaling via interrupt capabilities for all CAN

receiver and transmitter error states

• Programmable clock source

• Programmable link to timer module for

time-stamping and network synchronization

• Low-power Sleep and Idle mode

The CAN bus module consists of a protocol engine and

message buffering/control. The CAN protocol engine

handles all functions for receiving and transmitting

messages on the CAN bus. Messages are transmitted

by first loading the appropriate data registers. Status

and errors can be checked by reading the appropriate

registers. Any message detected on the CAN bus is

checked for errors and then matched against filters to

see if it should be received and stored in one of the

receive registers.

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