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Section 12. Input Capture

Input Capture

Figure 12-5: Time Period Measurement

12.5.2 Input Capture Operation with DMA

Some dsPIC33F family devices include a Direct Memory Access (DMA) module, which allows

data to be transferred from the Input Capture module to data memory without CPU intervention.

Refer to the specific dsPIC33F device data sheet to see if DMA exists on your particular device.

Refer to Section 22. “Direct Memory Access (DMA)” (DS70182) in the “dsPIC33F Family

Reference Manual” for more details on the DMA module.

When the Input Capture module and DMA channel are appropriately configured, the Input

Capture module issues a DMA request for every capture event. The DMA transfers data from the

Input Capture Buffer (ICxBUF) register into RAM, and issues a CPU interrupt after a predefined

number of transfers.

The DMA channel must be initialized with the following:

• The DMA Request Source Selection (IRQSEL<6:0>) bits in the DMA Request

(DMAxREQ<6:0>) register must select the DMA transfer request from Input Capture

module

• The DMA Channel Peripheral Address (DMAxPAD) register must be initialized with the

address of the Input Capture Buffer (ICxBUF) register

• The Transfer Direction (DIR) bit in DMA Control (DMAxCON<13>) register must be

cleared. In this condition, data is read from the peripheral and written to the dual port DMA

memory

In addition, the input capture interrupt bits must be cleared (ICI<1:0> = 00) to generate DMA

request for every capture event.

xxxx

1st Capture

Capture FIFO

xxxx

TMR2

TMR3

ICx

Capture

Event

Capture

Interrupt

(ICI<1:0> = 01)

Read captured

Value in ISR

Read captured

Value in ISR

2nd Capture

3rd Capture

4th Capture

Note: In this illustration, the Timer ramp is not to scale.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

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Microchip Technology dsPIC33F Family Manual de usuario Pagina 9

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