dsPIC33F/PIC24H Family Reference Manual
DS70205C-page 11-16 © 2010 Microchip Technology Inc.
11.6 32-BIT TIMER CONFIGURATION
A 32-bit Timer module can be formed by combining Type B and Type C 16-bit timers. For 32-bit
timer operation, the T32 control bit in the Type B Timer Control register (TxCON<3>) must be set.
The Type C timer holds the most significant word (msw) and the Type B timer holds the least
significant word (lsw) for 32-bit operation.
When configured for 32-bit operation, only the Type B Timer Control register bits are required for
setup and control. With the exception of the TSIDL bit, all Type C Timer Control register bits are
ignored. For more information, refer to 11.8.2 “Timer Operation in Idle Mode”.
For interrupt control, the combined 32-bit timer uses the interrupt enable, interrupt flag, and
interrupt priority control bits of the Type C timer. The interrupt control and status bits of the Type B
timer are ignored during 32-bit timer operation.
Table 11-2 lists the Type B and Type C timers that can be combined to form a 32-bit timer.
A block diagram representation of the 32-bit Timer module is shown in Figure 11-6. The 32-bit
Timer module can operate in any of the following modes:
•Timer
• Gated Timer
• Synchronous Counter
In Timer and Gated Timer modes, the input clock is derived from the internal instruction cycle
clock (F
CY). In Synchronous Counter mode, the input clock is derived from the Type B timer
external clock input at the TxCK pin.
The 32-bit Timer modes are determined by the following bits in the Type B Timer Control
registers:
• TCS (TxCON<1>): Timer Clock Source control bit
• TGATE (TxCON<6>): Timer Gate control bit
Timer control bit settings for different operating modes are provided in Table 11-3.
Table 11-2: 32-bit Timer Combinations
Type B Timer (lsw) Type C Timer (msw)
Timer2 Timer3
Timer4 Timer5
Timer6 Timer7
Timer8 Timer9
Table 11-3: Timer Mode Configuration
Mode
Bit Setting
TCS TGATE
Timer 00
Gated Timer 01
Synchronous Counter 1x
Note 1: Type B and Type C timers do not support the Asynchronous External Clock mode;
therefore, 32-bit Asynchronous Counter mode is not supported.
2: The PRx register resets on the subsequent rising edge of the timer clock input.
3: The TxIF bit is set one instruction cycle after a period match.
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