Microchip Technology dsPIC33F Family Manual de usuario descargar pdf (Pagina 9)

Section 11. Timers

Timers

R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0

TON

(2)

—TSIDL

(1)

— — — — —

bit 15 bit 8

U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0

— TGATE

(2)

TCKPS<1:0>

(2)

— —TCS

(2)

—

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 TON: Timerx On bit

(2)

1 = Starts 16-bit Timerx

0 = Stops 16-bit Timerx

bit 14 Unimplemented: Read as ‘0’

bit 13 TSIDL: Stop in Idle Mode bit

(1)

1 = Discontinue timer operation when device enters Idle mode

0 = Continue timer operation in Idle mode

bit 12-7 Unimplemented: Read as ‘0’

bit 6 TGATE: Timerx Gated Time Accumulation Enable bit

(2)

When TCS = 1:

This bit is ignored

When TCS =

1 = Gated time accumulation enabled

0 = Gated time accumulation disabled

bit 5-4 TCKPS<1:0>: Timerx Input Clock Prescale Select bits

(2)

11 = 1:256 prescale value

10 = 1:64 prescale value

01 = 1:8 prescale value

00 = 1:1 prescale value

bit 3-2 Unimplemented: Read as ‘0’

bit 1 TCS: Timerx Clock Source Select bit

(2)

1 = External clock from TxCK pin

0 = Internal clock (F

OSC/2)

bit 0 Unimplemented: Read as ‘0’

Note 1: When 32-bit timer operation is enabled (T32 = 1) in the Type B Timer Control register (TxCON<3>), the

TSIDL bit must be cleared to operate the 32-bit timer in Idle mode.

2: These bits have no effect when the 32-bit timer operation is enabled (T32 = 1) in the Type B Timer Control

1 2 3 4 5 6 7 8 9 10 11 12 13 14 ... 25 26

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Microchip Technology dsPIC33F Family Manual de usuario Pagina 9

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