Microchip Technology dsPIC33F Family Manual de usuario descargar pdf (Pagina 21)

Section 11. Timers

Timers

11.8 TIMER OPERATION IN POWER-SAVING MODES

11.8.1 Timer Operation in Sleep Mode

When the device enters Sleep mode, the system clock is disabled. If the Timer module is running

on the internal clock source (FCY), it is disabled as well.

A Type A timer is different from the other timers because it can operate asynchronously from the

system clock source. Because of this distinction, the Type A timer can continue to operate during

Sleep mode. To operate in Sleep mode, the Type A timer must be configured as follows:

• Clear the TSYNC control bit (TxCON<2>) to disable clock synchronization

• Set the TCS control bit (TxCON<1>) to select external clock source

• Enable the secondary oscillator, if the external clock input (TxCK) is not active

When all of these conditions are met, the timer continues to count and detect period matches

while the device is in Sleep mode. When a match between the timer and the period register

occurs, the TxIF bit is set. The timer interrupt is generated, if the timer interrupt is enabled

(TxIE = 1).

The timer interrupt wakes up the device from Sleep, and the following events occur:

• If the assigned priority level for the interrupt is less than, or equal to the current CPU

priority, the device wakes up and continues code execution from the instruction following

the PWRSAV instruction that initiated Sleep mode.

• If the assigned priority level for the interrupt source is greater than the current CPU priority,

the device wakes up and the CPU exception process begins. Code execution continues

from the first instruction of the timer Interrupt Service Routine (ISR).

For further details, refer to Section 9. “Watchdog Timer and Power-Saving Modes”

(DS70196).

11.8.2 Timer Operation in Idle Mode

When the device enters Idle mode, the system clock sources remain functional and the CPU

stops executing code. The Timer Stop-in Idle bit (TSIDL) in the Timer Control register

(TxCON<13>) determines whether the module stops in Idle mode or continues to operate in Idle

mode.

•If TSIDL=0, the timer continues to operate in Idle mode providing full functionality. For

32-bit timer operation, the TSIDL bit (TxCON<13>) must be cleared in Type B and Type C

Timer Control registers for a timer to operate in Idle mode.

•If TSIDL =1, the timer performs the same functions when stopped in Idle mode as in Sleep

mode (refer to 11.8.1 “Timer Operation in Sleep Mode”).

Note: The secondary oscillator is enabled by setting the Secondary Oscillator Enable bit

(LPOSCEN) in the Oscillator Control register (OSCCON<1>). For further details,

refer to Section 7. “Oscillator” (DS70186). The 32 kHz watch crystal must be

connected to the SOSCO/SOSCI device pins.

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Microchip Technology dsPIC33F Family Manual de usuario Pagina 21