
© 2010 Microchip Technology Inc. DS70205C-page 11-5
Section 11. Timers
Timers
11
11.2.3 Type C Timer
Timer3, Timer5, Timer7 and Timer9, if present, are Type C timers. A Type C timer has the
following specific features:
• It can be concatenated with a Type B timer to form a 32-bit timer.
• At least one Type C timer has the ability to trigger an Analog-to-Digital (A/D) conversion.
• The external clock input (TxCK) is always synchronized to the internal device clock. The
clock synchronization is performed using TxCK, after which this synchronized clock is
divided by the prescaler.
Figure 11-3 shows a block diagram of the Type C timer.
Figure 11-3: Type C Timer Block Diagram
TGATE
TCS
00
10
x1
TMRx
Comparator
PRx
TGATE
Set TxIF Flag
0
1
Sync
Equal
Reset
Prescaler
(/n)
TCKPS<1:0>
Gate
Sync
FCY
(1)
Falling Edge
Detect
Prescaler
(/n)
TCKPS<1:0>
Latch
CLK
DATA
TXCK
ADC Start of
Conversion Trigger
(2)
Note 1: FCY is the instruction cycle clock.
2: ADC trigger is only available on TMR3 and TMR5.
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